Bhagwan Das Ahirwar
M.Tech., IIT JammuAssistant Professor, School of Engineering
Bhagwan Das Ahirwar
M.Tech., IIT JammuMy research work is focused on providing the security of IEEE 1838 based testing architecture used in 2.5D and 3D chiplet systems. As chiplet based design is becoming popular for developing complex integrated circuits / System in Package (SiP), secure testing has become an important challenge. During post integration testing, the test data of tier 3 chiplet may pass through another tier 2 chiplet inside the package (chiplets are stacked in 3D). Due to delivery time, untrusted vendor chiplet may be procured. If tier 2 chiplet is untrusted, it can observe, modify, or misuse the scan communication data passing through it and targeted chiplet 3. The IEEE 1838 standard provides an efficient test access architecture for chiplet systems, but it does not provide any direct hardware security mechanism to protect the scan and configuration data.
In this research, I studied the existing secure testing techniques proposed by other scholar for IEEE 1838 based systems and analyzed their advantages and limitations. Most of the existing techniques provide strong security but require very high overhead hardware resources and increase implementation complexity. Therefore, I focused to develop a lightweight security solution that can provide scan communication protection with lower hardware overhead.
The proposed work uses an on chip PUF to generate the seed for a 128-bit Non-Linear Feedback Shift Register (NLFSR). The generated NLFSR sequence is used in a stream cipher block to decipher the ciphertext. In addition, a CRC-32 based tamper checking mechanism is used to verify the integrity of transmitted scan data and detect unauthorized modifications. An 8-bit down counter controls different phases of operation, including initialization, secure communication, and final locking operation.
The complete architecture is designed using Verilog HDL and implemented on the Xilinx Vivado platform and synthesize using Cadence genus using 45 nm technology node. The obtained results show that the proposed architecture provides secure scan data and configuration data while requiring lower hardware resources compared to existing secure testing approaches. Through this work, I aim to contribute towards the development of lightweight and practical security solutions for future chiplet based integrated circuits.
Bhagwan Das Ahirwar has completed his Master of Technology (M.Tech.) degree in VLSI Design from the Indian Institute of Technology Jammu. He earned his Bachelor of Technology (B.Tech.) degree in Electronics and Communication Engineering from Rajiv Gandhi Proudyogiki Vishwavidyalaya (RGPV), Bhopal. He qualified the Graduate Aptitude Test in Engineering (GATE).
He has more than ten years of industrial experience and was working as a Management – Engineer at Jones Lang LaSalle (JLL). During his professional career, he has been involved in engineering operations, project management, technical support, and maintenance activities of Electro-Mechanical equipment.
His research interests include VLSI testing, hardware security, Design-for-Testability (DfT), IEEE 1838 based chiplet testing, FPGA implementation, and secure scan communication architectures. His M.Tech. research focused on developing a lightweight secure testing architecture for IEEE 1838 compliant 2.5D and 3D chiplet systems using on chip PUF assisting to NLFSR based stream cipher and CRC based tamper detection technique. He is interested in developing practical and low overhead security architecture for 3D chiplet testing including detecting the modification and correcting it
- M.Tech., VLSI Design, 2026, Indian Institute of Technology Jammu
- B.E., Electronics and Communication Engineering, RGPG Bhopal
Project 1
- Title: Thesis : IEEE 1838 standard secure test architecture
- Duration: June 2025 to June 2026
- Granting Agency – IIT Jammu
- PIs/Co PIs:
- Purpose – M.Tech. Thesis
- Short Description – It provides the secure testing architecture in 3D stack ic configuration
- Status: Completed
- Grant Amount: NA
Project 2
- Title: MIPS single cycle, multi cycle and pipeline processors implementation using Verilog HDL.
- Duration: Jan 2025 to May 2025
- Granting Agency – IIT Jammu
- PIs/Co PIs:
- Purpose – Computer Architecture course project
- Short Description – Processors implemented with basic instruction by using Verilog HDL.
- Status: Completed
- Grant Amount: NA
LinkedIn – Bhagwan Ahirwar | LinkedIn
Github – Bhagwan-Ahirwar (Bhagwan)
- Executed multiple projects during my industry career. It includes UPS installation (Purchasing to sign off), HVAC unit installation, IAQ equipment installations, small scale interior project of the corporate offices.
- Prepare the budget for opex and capex of corporate office.
- Run end to end admin services.